-- EASE/HDL begin --------------------------------------------------------------
-- 
-- Architecture 'structure' of entity 'FSM_dec'.
-- 
--------------------------------------------------------------------------------
-- 
-- Copy of the interface declaration:
-- 
--   port(
--     DCF_sig       : in     std_logic;
--     DCF_sig_dem   : out    std_logic;
--     Min_Begin_ebl : out    std_logic;
--     Sig_Error     : out    std_logic;
--     clk           : in     std_logic;
--     clk_100       : in     std_logic;
--     reset_n       : in     std_logic;
--     shift_ebl     : out    std_logic);
-- 
-- EASE/HDL end ----------------------------------------------------------------

architecture structure of FSM_dec is


SIGNAL sync1DCF_sig : std_logic;
SIGNAL sync2DCF_sig : std_logic;
SIGNAL sync3DCF_sig : std_logic;

SIGNAL counter : std_logic_vector(7 downto 0);



BEGIN 
P_sync:PROCESS(clk, reset_n)  
BEGIN 
    IF reset_n = '0' THEN 
      sync1DCF_sig <= '0'; 
      sync2DCF_sig <= '0'; 
      sync3DCF_sig <= '0'; 
    ELSIF clk'EVENT AND clk = '1' THEN 
      sync1DCF_sig <= DCF_sig; 
      sync2DCF_sig <= sync1DCF_sig; 
      sync3DCF_sig <= sync2DCF_sig; 
    END IF;
END PROCESS;


P_dem:PROCESS(clk, reset_n, DCF_sig)  
BEGIN 
    IF reset_n = '0' THEN 
      counter <= (OTHERS => '0');
      DCF_sig_dem <= '0';
      shift_ebl <= '0';
      Sig_Error <= '0';
      Min_Begin_ebl <= '0';
    ELSIF clk'EVENT AND clk = '1' THEN 
      IF ((sync2DCF_sig XOR sync3DCF_sig) = '1') AND (sync2DCF_sig = '1') THEN -- front montant sur sync3DCF_sig
      	 IF (counter(7) = '1' ) THEN --si le counter atteind 128 (1280ms) et que le signal DCF est 
      		Min_Begin_ebl <= '1';
      	 END IF;
      	 counter <= (OTHERS => '0');
      	 DCF_sig_dem <= '0';
      ELSE
      	 Min_Begin_ebl <= '0';
      END IF;
                                                 
      IF (counter = "00001111") AND (sync3DCF_sig = '1') THEN --si le counter atteind 15 (150ms) et que le signal DCF est 
      	DCF_sig_dem <= '1';
      END IF;
      
      IF (counter = "01010000" AND clk_100 = '1')  THEN --si le counter atteind 80 (800ms) -> shift
      	 shift_ebl <= '1';
      ELSE
      	 shift_ebl <= '0';
      END IF;
      IF(clk_100 = '1')THEN     
      	  counter <= UNSIGNED(counter) + 1;
      END IF;
      IF (counter = "11111111")THEN
      		Sig_Error <= '1';
      ELSE
      		Sig_Error <= '0';
      END IF;
    END IF;
END PROCESS;
end architecture structure ; -- of FSM_dec

